Direct memory access (DMA) is used by computer systems to enable hardware subsystems to access main system memory independently of the central processing unit (CPU). Without DMA, when the CPU is managing programmed input/output memory operations, the CPU is typically fully occupied for the entire duration of a read or write operation, such that the CPU is unavailable to perform other work. With conventional DMA, the CPU first initiates the memory transfer, then it does other operations while the transfer is in progress, and it finally receives an interrupt from the DMA controller when the operation is done.
DMA is also useful at times that the CPU cannot keep up with a rate of data transfer, or when the CPU needs to perform useful work while waiting for a relatively slow input/output (I/O) data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA may also be used for intra-chip data transfer in multi-core processors. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels. Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel.
While DMA can significantly lower the burden involved in data transactions on the CPU, a CPU that needs information must still issue a transaction request to the DMA controller instructing the DMA controller to execute the I/O data transfer (e.g., fetch data from storage). In a typical case, a DMA engine has a set of registers that the CPU must set to values that specify the operation to be carried out by the DMA engine. Once this specification is complete, the DMA engine can carry out a task independently, without further intervention of the CPU. When that single task is complete, however, the CPU must again load the DMA engine's registers with appropriate values to carry out another task. The CPU also must still collect the results from memory, moving the data from memory into its execution registers after it receives an interrupt from the DMA controller indicating that the data is available (i.e., that the I/O fetch operation is complete).
Thus, although the use of DMA can significantly reduce the data bottleneck associated with I/O transactions, the CPU must still interrupt other tasks to carry out operations related to data transfers. Furthermore, these interruptions typically have a substantial cost. The CPU typically needs to save its current state, set up the DMA transfer, and restore the saved state to go back to executing the task that was being accomplished before the interruption took place.